View CXK77Q36162GB_1152102.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16mb ddr1, rev 1.0 1 / 24 july 3 , 200 2 CXK77Q36162GB sony 25/27/3 16mb ddr1 hstl high speed synchronous sram ( 512k x 36 ) preliminary description features ? 3 speed bins cycle time / access time data rate -25 2.5ns / 1.8ns 800 mbps -27 2.7ns / 1.9ns 740 mbps -3 3.0ns / 2.0ns 666 mbps ? single 2.5v power supply (v dd ): 2.5v 5% ? dedicated output supply voltage (v ddq ): 1.5v 0.1v ? hstl-compatible i/o interface with dedicated input reference voltage (v ref ): 0.75v typical ? ddr1 functional compatibility ? register - register (r-r) read protocol ? late write (lw) write protocol ? single data rate (sdr) and double data rate (ddr) data transfers ? burst capability via continue commands ? linear or interleaved burst order, selectable via dedicated mode pin ( lbo ) ? full read/write coherency ? two cycle deselect ? differential input clocks (ck/ ck ) ? positive and negative output clocks (cq/ cq ) - one pair per 18 bits of output data (dq) ? asynchronous output enable ( g ) ? programmable output driver impedance ? jtag boundary scan (subset of ieee standard 1149.1) ? 153 pin (9x17), 1.27mm pitch, 14mm x 22mm ball grid array (bga) package the CXK77Q36162GB is a high speed cmos synchronous static ram with common i/o pins, organized as 524,288 words by 36 bits. this synchronous sram integrates input registers, high speed ram, output registers, and a two-deep write buffer onto a single monolithic ic. single data rate (sdr) and double data rate (ddr) register - register (r-r) read operations and late write (lw) write operations are supported, providing a flexible, high-performance user interface. continue operations are supported, providing burst capability. positive and negative output clocks are provided for applications requiring source- synchronous operation. all address and control input signals except the g output enable signal are registered on the rising edge of the ck differential input clock. all commands are input via the b(1:3) control signals. during sdr read operations, output data is driven valid once, from the rising edge of ck, one full clock cycle after the address is registered. during ddr read operations, output data is driven valid twice, first from the rising edge of ck and then from the falling edge of ck, beginning one full clock cycle after the address is registered. in both cases, output data transitions are c losely aligned with output clock transitions. during sdr write operations, input data is registered once, on the rising edge of ck, one full clock cycle after the address is registered. during ddr write operations, input data is registered twice, first on the rising edge of ck and then on the falling edge of ck, beginning one full clock cycle after the address is registered. output drivers are series terminated, and output impedance is programmable via the zq input pin. by connecting an external control resistor rq between zq and v ss , the impedance of all data and clock output drivers can be precisely controlled. 400 mhz operation (800 mbps) is obtained from a single 2.5v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 2 / 24 july 3 , 200 2 pin assignment (top view) notes: 1. pad location 6l is a true no-connect. however, it may be defined as a mode pin in future versions of ddr srams. 2. pad location 7u must be left unconnected. it is used by sony for internal test purposes. 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq dq sa v ss b1 v ss sa dq dq c v ss v ddq sa sa g sa sa v ddq v ss d dq dq sa v ss v dd v ss sa dq dq e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq cq dq v dd v dd v dd dq cq dq g v ss v ddq v ss v ss ck v ss v ss v ddq v ss h dq dq dq v dd ck v dd dq dq dq j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq dq dq v ss b2 v ss dq dq dq l v ss v ddq v ss lbo b3 nc (1) v ss v ddq v ss m dq cq dq v dd v dd v dd dq cq dq n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq dq nc (x18) v ss v dd v ss sa dq dq r v ss v ddq v dd sa sa1 sa v dd v ddq v ss t dq dq sa v ss sa0 v ss sa dq dq u v ss v ddq tms tdi tck tdo rsvd (2) v ddq v ss
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 3 / 24 july 3 , 200 2 pin description symbol type description sa input synchronous address inputs - registered on the rising edge of ck. sa1, sa0 input synchronous address inputs (1:0) - registered on the rising edge of ck. initialize burst counter. dq i/o synchronous data inputs / outputs - registered on the rising edge of ck during sdr write opera- tions. registered on the rising and falling edges of ck during ddr write operations. driven from the rising edge of ck during sdr read operations. driven from the rising and falling edges of ck during ddr read operations. ck, ck input differential input clocks cq, cq i/o output clocks b1, b2, b3 input synchronous control inputs (1:3) - registered on the rising edge of ck. specify the type of opera- tion (sdr read, sdr write, ddr read, ddr write, continue, or deselect) to be executed by the sram. see the clock truth table and state diagram sections for further information. g input asynchronous output enable input - deasserted (high) disables the data output drivers. lbo input burst order select input - this mode pin must be tied ?high? or ?low? at power-up. lbo = 0 selects linear burst order lbo = 1 selects interleaved burst order zq input output impedance control resistor input - this pin must be connected to v ss through an external resistor rq to program data and clock output driver impedance. see the programmable output driver impedance section for further information. v dd 2.5v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ref input reference voltage - input buffer threshold voltage. v ss ground tck input jtag clock tms input jtag mode select - weakly pulled ?high? internally. tdi input jtag data in - weakly pulled ?high? internally. tdo output jtag data out rsvd reserved - this pin is used for sony test purposes only. it must be left unconnected. nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd , v ddq , or v ss .
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 4 / 24 july 3 , 200 2 clock truth table ck b1 (t n ) b2 (t n ) b3 (t n ) previous operation current operation dq (t n ) dq (t n+? ) dq (t n+1 ) dq (t n+1? ) 0 ? 1 0 1 1 --- single data rate read load new address x q1(t n ) 0 ? 1 0 1 0 --- double data rate read load new address x x q1(t n ) q2(t n ) 0 ? 1 0 0 1 --- single data rate write load new address flush write buffer x d1(t n ) 0 ? 1 0 0 0 --- double data rate write load new address flush write buffer x x d1(t n ) d2(t n ) 0 ? 1 1 1 x sdr read single data rate read continue increment address by one q1(t n-1 ) q2(t n ) 0 ? 1 1 1 x ddr read double data rate read continue increment address by two q1(t n-1 ) q2(t n-1 ) q3(t n ) q4(t n ) 0 ? 1 1 1 x sdr write single data rate write continue increment address by one flush write buffer d1(t n-1 ) d2(t n ) 0 ? 1 1 1 x ddr write double data rate write continue increment address by two flush write buffer d1(t n-1 ) d2(t n-1 ) d3(t n ) d4(t n ) 0 ? 1 1 0 x not deselect deselect x hi - z 0 ? 1 1 x x deselect deselect (continue) hi - z hi - z state diagram power up deselect sdr read sdr write ddr read ddr write load new address increment address by one increment address by one increment address by two increment address by two b1.b2 b1.b2 b1.b2 b1.b2 b1. b2 b2 .b3 b1 b1 b2 . b3 b2. b3 flush wb flush wb b1 b2.b3 b1 flush wb b1 b1. b2 b1. b2 b1. b2 b1
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 5 / 24 july 3 , 200 2 ? continue operations these devices support continue (burst) operations via the synchronous b(1:3) control input signals. they have the ability to burst transfer a maximum of four (4) distinct pieces of data per single external address input, regardless whether the data transfers are sdr or ddr. sdr read and write operations transfer one (1) piece of data. consequently, one (1), two (2), or three (3) continue opera- tions may be initiated immediately after an sdr read or write operation to burst transfer two (2), three (3), or four (4) dis- tinct pieces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal address wraps back to the initial external (base) address. ddr read and write operations transfer two (2) pieces of data. consequently, one (1) continue operation may be initiated immediately after a ddr read or write operation to burst transfer four (4) distinct pieces of data per single external address input. if a second (2nd) continue operation is initiated, the internal address wraps back to the initial external (base) address . the order (i.e. address sequence) in which multiple pieces of data are transferred during ddr and/or continue operations is determined by the state of lbo mode pin. when lbo = 1, data transfers follow the interleaved burst address sequence depicted in the table below: when lbo = 0, data transfers follow the linear burst address sequence depicted in the table below:. ? programmable impedance output drivers these devices have programmable impedance output drivers. the output impedance is controlled by an external resistor rq connected between the sram?s zq pin and v ss , and is equal to one-fifth the value of this resistor, nominally. see the dc electrical characteristics section for further information. output driver impedance power-up requirements output driver impedance will reach the programmed value within 8192 cycles after power-up. consequently, it is recom- mended that read operations not be initiated until after the initial 8192 cycles have elapsed. output driver impedance updates data output impedance is updated during write and deselect operations when the output driver is disabled. clock pull-up output impedance is updated during write and deselect operations when the output driver is driving ?low?. clock pull-down output impedance is updated during write and deselect operations when the output driver is driving ?high?. interleaved burst address sequence address sequence sa(1:0) sequence key 1st (base) address 00 01 10 11 sa1, sa0 2nd address 01 00 11 10 sa1, sa0 3rd address 10 11 00 01 sa1 , sa0 4th address 11 10 01 00 sa 1, sa0 linear burst address sequence address sequence sa(1:0) sequence key 1st (base) address 00 01 10 11 sa1, sa0 2nd address 01 10 11 00 (sa1 xor sa0), sa0 3rd address 10 11 00 01 sa1 , sa0 4th address 11 00 01 10 (sa1 xor sa0) , sa0
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 6 / 24 july 3 , 200 2 ? power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq should never exceed v dd . if this power supply sequence cannot be met, a large bypass diode may be re- quired between v dd and v ddq . please contact sony memory application department for further information. ? absolute maximum ratings note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ? bga package thermal characteristics ? i/o capacitance (t a = 25 o c, f = 1 mhz) note : these parameters are sampled and are not 100% tested. parameter symbol rating units supply voltage v dd -0.5 to +3.0 v output supply voltage v ddq -0.5 to +2.3 v input voltage (address, control, data, clock) v in -0.5 to v ddq +0.5 (2.3v max) v input voltage ( lbo ) v min -0.5 to v ddq +0.5 (2.3v max) v input voltage (tck, tms, tdi) v tin -0.5 to v dd +0.5 (3.0v max) v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c parameter symbol rating units junction to case temperature q jc 1.0 c/w parameter symbol test conditions min max units input capacitance address c in v in = 0v --- 4.2 pf control c in v in = 0v --- 4.2 pf ck clock c kin v kin = 0v --- 3.5 pf output capacitance data c out v out = 0v --- 4.8 pf cq clock c out v out = 0v --- 4.8 pf
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 7 / 24 july 3 , 200 2 ? dc recommended operating conditions (v ss = 0v, t a = 0 to 85 o c) 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component. 2. v ih (max) ac = v ddq + 0.75v for pulse widths less than one-quarter of the cycle time (t cyc /4). 3. v il (min) ac = -0.75v for pulse widths less than one-quarter of the cycle time (t cyc /4). parameter symbol min typ max units notes supply voltage v dd 2.37 2.5 2.63 v output supply voltage v ddq 1.4 1.5 1.6 v input reference voltage v ref 0.65 0.75 0.85 v 1 input high voltage (address, control, data) v ih v ref + 0.2 --- v ddq + 0.3 v 2 input low voltage (address, control, data) v il -0.3 --- v ref - 0.2 v 3 input high voltage ( lbo ) v mih v ref + 0.3 --- v ddq + 0.3 v input low voltage ( lbo ) v mil -0.3 --- v ref - 0.3 v clock input signal voltage v kin -0.3 --- v ddq + 0.3 v clock input differential voltage v dif 0.2 --- v ddq + 0.6 v clock input common mode voltage v cm 0.65 0.75 0.85 v
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 8 / 24 july 3 , 200 2 ? dc electrical characteristics (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 o c) 1. for maximum output drive (i.e. minimum impedance), the zq pin can be tied directly to v ss . 2. for minimum output drive (i.e. maximum impedance), the zq pin can be left unconnected or tied to v ddq . parameter symbol test conditions min typ max units notes input leakage current (address, control, clock) i li v in = v ss to v ddq -5 --- 5 ua input leakage current ( lbo ) i mli v min = v ss to v ddq -10 --- 10 ua output leakage current i lo v din = v ss to v ddq g = v ih -10 --- 10 ua average power supply operating current i dd i out = 0 ma v in = v ih or v il t cyc = 275 mhz --- --- 750 ma output high voltage v oh i oh = -6.0 ma rq = 250 w v ddq - 0.4 --- --- v output low voltage v ol i ol = 6.0 ma rq = 250 w --- --- 0.4 v output driver impedance r out v oh , v ol = v ddq /2 rq < 150 w --- --- 35 (30*1.15) w 1 v oh , v ol = v ddq /2 150 w rq 300 w (rq/5)* 0.85 rq/5 (rq/5)* 1.15 w v oh , v ol = v ddq /2 rq > 300 w 51 (60*0.85) --- --- w 2
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 9 / 24 july 3 , 200 2 ? ac electrical characteristics (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 o c) 1. these parameters are guaranteed by design through extensive corner lot characterization. 2. these parameters are measured at 50mv from steady state voltage. parameter symbol -25 -27 -3 units notes min max min max min max input clock cycle time t khkh 2.5 --- 2.7 --- 3.0 --- ns input clock high pulse width input clock low pulse width t khkl t klkh 1.0 --- 1.1 --- 1.2 --- ns address input setup time t avkh 0.35 --- 0.35 --- 0.35 --- ns 1 address input hold time t khax 0.35 --- 0.35 --- 0.35 --- ns 1 control input setup time t bvkh 0.35 --- 0.35 --- 0.35 --- ns 1 control input hold time t khbx 0.35 --- 0.35 --- 0.35 --- ns 1 data input setup time t dvkh t dvkl 0.25 --- 0.25 --- 0.3 --- ns 1 data input hold time t khdx t kldx 0.25 --- 0.25 --- 0.3 --- ns 1 input clock high to output data valid input clock low to output data valid t khqv t klqv --- 1.8 ---- 1.9 --- 2.0 ns input clock high to output data hold input clock low to output data hold t khqx t klqx 0.5 --- 0.5 --- 0.5 --- ns 1 input clock high to output data low-z t khqx1 0.5 --- 0.5 --- 0.5 --- ns 1,2 input clock high to output data high-z t khqz --- 1.8 ---- 1.9 --- 2.0 ns 1,2 input clock cross to output clock high input clock cross to output clock low t kxch t kxcl 0.5 1.8 0.5 1.9 0.5 2.0 ns output clock high to output data valid output clock low to output data valid t chqv t clqv --- 0.2 --- 0.2 --- 0.2 ns 1 output clock high to output data hold output clock low to output data hold t chqx t clqx -0.2 --- -0.2 --- -0.2 --- ns 1 output clock high pulse width t chcl t khkl 0.1 t khkl 0.1 t khkl 0.1 ns 1 output clock low pulse width t clch t klkh 0.1 t klkh 0.1 t klkh 0.1 ns 1 output enable low to output valid t glqv --- 1.8 ---- 1.9 --- 2.0 ns output enable low to output low-z t glqx 0.3 --- 0.3 --- 0.3 --- ns 1,2 output enable high to output high-z t ghqz --- 1.8 --- 1.9 --- 2.0 ns 1,2
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 10 / 24 july 3 , 200 2 ? ac electrical characteristics (note) the four ac timing parameters listed below are tested according to specific combinations of output clocks and output data: 1. t chqv - output clock high to output data valid (max) 2. t clqv - output clock low to output data valid (max) 3. t chqx - output clock high to output data hold (min) 4. t clqx - output clock low to output data hold (min) the specific cq / dq combinations are defined as follows: cqs dqs 2f, 8m 1d, 1h, 1m, 1t, 2b, 2k, 2p, 3h, 3m, 7f, 7k, 8d, 8h, 8t, 9b, 9f, 9k, 9p 2m, 8f 1b, 1f, 1k, 1p, 2d, 2h, 2t, 3f, 3k, 7h, 7m, 8b, 8k, 8p, 9d, 9h, 9m, 9t
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 11 / 24 july 3 , 200 2 ? ac test conditions (v dd = 2.5v 5%, v ddq = 1.5v 0.1v, t a = 0 to 85 c ) item symbol conditions units notes input reference voltage v ref 0.75 v input high level v ih 1.25 v input low level v il 0.25 v input rise & fall time 2.0 v/ns input reference level 0.75 v clock input high voltage v kih 1.25 v v dif = 1.0v clock input low voltage v kil 0.25 v v dif = 1.0v clock input common mode voltage v cm 0.75 v clock input rise & fall time 2.0 v/ns clock input reference level ck/ ck cross v output reference level 0.75 v output load conditions rq = 250 w see figure 1 below dq 0.75 v figure 1: ac test output load (v ddq = 1.5v) 50 w 50 w 5 pf 16.7 w 0.75 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 12 / 24 july 3 , 200 2 timing diagram of double data rate (ddr) read-write-read operations synchronously controlled via deselect operations ( g = low) note : in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the applica- tion, one deselect operation may be sufficient. a2 a3 a4 a5 11x 010 10x 000 11x 000 010 10x 1xx ck ck sa b(1:3) 010 1xx t khax t avkh t khbx t bvkh a1 read read continue read deselect deselect write write continue write read deselect deselect figure 2 dq t khdx t dvkh cq cq g = v il t kxcl t kxch t chcl t clch t khqx1 t khqz d33 d34 d41 d42 d31 d32 t kldx t dvkl q11 q12 q13 q14 q21 q22 q51 q52 t klqv t klqx t khqv t khqx t clqx t clqv t chqx t chqv t khkh t khkl t klkh
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 13 / 24 july 3 , 200 2 timing diagram of single data rate (sdr) read-write-read operations synchronously controlled via deselect operations ( g = low) note : in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the applica- tion, one deselect operation may be sufficient. a2 a3 a4 a5 11x 011 10x 001 11x 001 011 10x 1xx ck ck sa b(1:3) 011 1xx t khax t avkh t khbx t bvkh a1 read read continue read deselect deselect write write continue write read deselect deselect figure 3 dq t khdx t dvkh cq cq g = v il t kxcl t kxch t chcl t clch t khqx1 t khqz d32 d41 d31 t khqv t khqx t chqx t chqv t khkh t khkl t klkh q11 q12 q21 q51
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 14 / 24 july 3 , 200 2 timing diagram of double data rate (ddr) read-write-read operations asynchronously controlled via g and dummy read operations note : in the diagram above, two dummy read operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one dummy read operation may be sufficient. a2 a3 a4 a5 11x 010 010 000 11x 000 010 10x 010 ck ck sa b(1:3) 010 1xx t khax t avkh t khbx t bvkh a1 read read continue read read read write write continue write read deselect deselect figure 4 dq t khdx t dvkh cq cq g t kxcl t kxch t chcl t clch t khqx1 t khqz d33 d34 d41 d42 d31 d32 t kldx t dvkl q11 q12 q13 q14 q21 q22 q51 q52 t klqv t klqx t khqv t khqx t clqx t clqv t chqx t chqv t khkh t khkl t klkh t glqv t glqx t ghqz dummy dummy
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 15 / 24 july 3 , 200 2 timing diagram of single data rate (sdr) read-write-read operations asynchronously controlled via g and dummy read operations note : in the diagram above, two dummy read operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one dummy read operation may be sufficient. a2 a3 a4 a5 11x 011 011 001 11x 001 011 10x 011 ck ck sa b(1:3) 011 1xx t khax t avkh t khbx t bvkh a1 read read continue read read read write write continue write read deselect deselect figure 5 cq cq g t kxcl t kxch t chcl t clch t khqx1 t khqz t khqv t khqx t chqx t chqv t khkh t khkl t klkh t glqv t glqx t ghqz dq t khdx t dvkh d32 d41 d31 q11 q12 q21 q51 dummy dummy
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 16 / 24 july 3 , 200 2 ? test mode description these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, con- troller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, this device contains a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied ?low? to prevent clocking the sram. tms and tdi should either be tied ?high? through a pull-up resistor or left unconnected. tdo should be left unconnected. note : operation of the tap does not interfere with normal sram operation except when the sample-z instruction is se- lected. consequently, tck, tms, and tdi can be controlled any number of ways without adversely affecting the function- ality of the device. jtag dc recommended operating conditions (v dd = 2.5v 5%, t a = 0 to 85 c ) jtag ac test conditions (v dd = 2.5v 5%, t a = 0 to 85 c ) parameter symbol test conditions min max units jtag input high voltage v tih --- 1.4 v dd + 0.3 v jtag input low voltage v til --- -0.3 0.8 v jtag output high voltage (cmos) v toh i toh = -100ua v dd - 0.1 --- v jtag output low voltage (cmos) v tol i tol = 100ua --- 0.1 v jtag output high voltage (ttl) v toh i toh = -4.0ma v dd - 0.4 --- v jtag output low voltage (ttl) v tol i tol = 4.0ma --- 0.4 v jtag input leakage current i tli v tin = v ss to v dd -10 10 ua parameter symbol conditions units notes jtag input high level v tih 2.5 v jtag input low level v til 0.0 v jtag input rise & fall time 1.0 v/ns jtag input reference level 1.25 v jtag output reference level 1.25 v jtag output load condition see fig.1 (page 11)
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 17 / 24 july 3 , 200 2 jtag ac electrical characteristics jtag timing diagram parameter symbol min max unit tck cycle time t thth 100 ns tck high pulse width t thtl 40 ns tck low pulse width t tlth 40 ns tms setup time t mvth 10 ns tms hold time t thmx 10 ns tdi setup time t dvth 10 ns tdi hold time t thdx 10 ns tck low to tdo valid t tlqv 20 ns tck low to tdo hold t tlqx 0 ns figure 6 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 18 / 24 july 3 , 200 2 tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the operations associated with each tap instruction. state transitions are controlled by tms and occur on the rising edge of tck . the tap controller enters the ?test-logic reset? state in one of two ways: 1. at power up. 2. when a logic ?1? is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. the tdo output driver is active only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. tap controller state diagram figure 7 test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 19 / 24 july 3 , 200 2 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they are divided into two groups: ?instruction registers? (ir), which are manipulated via the ?ir? states in the tap controller, and ?data registers? (dr), which are manipulated via the ?dr? states in the tap controller. instruction register (ir - 3 bits) the instruction register stores the various tap instructions supported by these devices. it is loaded with the idcode in- struction at power-up, and when the tap controller is in the ?test-logic reset? and ?capture-ir? states. it is inserted be- tween tdi and tdo when the tap controller is in the ?shift-ir? state, at which time it can be loaded with a new instruction. however, newly loaded instructions are not executed until the tap controller has reached the ?update-ir? state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb of the instruction register, and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. bypass register (dr - 1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic ?0? when the bypass instruction has been loaded in the instruction register and the tap controller is in the ?cap- ture-dr? state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction reg- ister and the tap controller is in the ?shift-dr? state. code (2:0) instruction description 000 bypass see code ?111?. 001 idcode loads a predefined device- and manufacturer-specific identification code into the id register when the tap controller is in the ?capture-dr? state, and inserts the id register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the id register description for more information. 010 sample-z captures the individual logic states of all address, control, data, and clock signals in the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the boundary scan register between tdi and tdo when the tap controller is in the ?shift- dr? state. also disables the data and clock output drivers. see the boundary scan register description for more information. 011 bypass see code ?111?. 100 sample captures the individual logic states of all address, control, data, and clock signals in the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the boundary scan register between tdi and tdo when the tap controller is in the ?shift- dr? state. see the boundary scan register description for more information. 101 private do not use. reserved for manufacturer use only. 110 bypass see code ?111?. 111 bypass loads a logic ?0? into the bypass register when the tap controller is in the ?capture-dr? state, and inserts the bypass register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the bypass register description for more information.
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 20 / 24 july 3 , 200 2 id register (dr - 32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the id register is 32 bits wide, and is encoded as follows: bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. boundary scan register (dr - 68 bits) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for density and/or functional upgrades. the boundary scan register is loaded with the contents of the sram?s i/o ring when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?shift- dr? state. the boundary scan register contains the following bits: note : for deterministic results, all signals composing the sram?s i/o ring must meet setup and hold times with respect to tck (same as tdi and tms) when sampled. note : ck and ck are connected to a differential input receiver that generates a single-ended input clock signal to the device. therefore, in order to capture specific values for these signals in the boundary scan register, these signals must be at oppo- site logic levels when sampled. note : when an external resistor rq is connected between the zq pin and v ss , the value of the zq signal captured in the boundary scan register is non-deterministic. note : place holders are required for some nc pins to allow for future density and/or functional upgrades. they are connect- ed to v dd internally, regardless of pin connection externally. revision number (31:28) part number (27:12) sony id (11:1) start bit (0) xxxx 0000 0000 0100 1100 0000 1110 001 1 dq 36 sa, sa1, sa0 19 ck, ck 2 cq, cq 4 b1, b2, b3 3 g 1 lbo , zq 2 place holder 1
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 21 / 24 july 3 , 200 2 boundary scan register bit order assignments the table below depicts the order in which bits are arranged in the boundary scan register. bit 1 is the lsb and bit 68 is the msb. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. note 1 : nc pin at pad location 6l is connected to v dd internally, regardless of pin connection externally. bit signal pad bit signal pad 1 sa1 5r 35 sa 6a 2 sa0 5t 36 sa 4a 3 sa 6r 37 sa 4c 4 sa 7t 38 sa 3a 5 sa 7p 39 sa 3b 6 dq 8t 40 sa 3c 7 dq 9t 41 sa 3d 8 dq 8p 42 dq 2b 9 dq 7m 43 dq 1b 10 dq 9p 44 dq 2d 11 cq 8m 45 dq 3f 12 dq 9m 46 dq 1d 13 dq 7k 47 cq 2f 14 dq 8k 48 dq 1f 15 dq 9k 49 dq 3h 16 nc (1) 6l 50 dq 2h 17 ck 5h 51 dq 1h 18 ck 5g 52 zq 5a 19 g 5c 53 b1 5b 20 dq 9h 54 b2 5k 21 dq 8h 55 b3 5l 22 dq 7h 56 lbo 4l 22 dq 9f 57 dq 1k 24 cq 8f 58 dq 2k 25 dq 9d 59 dq 3k 26 dq 7f 60 dq 1m 27 dq 8d 61 cq 2m 28 dq 9b 62 dq 1p 29 dq 8b 63 dq 3m 30 sa 7d 64 dq 2p 31 sa 7c 65 dq 1t 32 sa 7b 66 dq 2t 33 sa 7a 67 sa 3t 34 sa 6c 68 sa 4r
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 22 / 24 july 3 , 200 2 ? ordering information part number v dd i/o type size speed (cycle time / access time) CXK77Q36162GB-25 2.5v hstl 512k x 36 2.5ns / 1.8ns CXK77Q36162GB-27 2.5v hstl 512k x 36 2.7ns / 1.9ns CXK77Q36162GB-3 2.5v hstl 512k x 36 3.0ns / 2.0ns sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illus - trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuit s.
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 23 / 24 july 3 , 200 2 153 pin bga package dimensions a b 10.16 1.27 153 - f 0.75 0.15 s ab 1 2 3 4 5 6 7 a b c d e f g h j k l m n p r t u f 0.15 m 8 9 preliminary 2 0 . 3 2 sony code eiaj code jedec code package material borad treatment lead material package mass solder package structure bga-153p-021 bga153-p-1422 epoxy resin copper-clad laminate 1.5g 13.0 x4 2.5 max 0.6 0.1 s s 14.0 s a 0.15 0.15 0.20 4 - c 0 . 7 4 - c 1 . 0 1 9 . 0 2 2 . 0 0 . 1 5 s b 0 . 3 5 s / /
sony ? CXK77Q36162GB preliminary 16mb ddr1, rev 1.0 24 / 24 july 3 , 200 2 ? revision history rev. # rev. date description of modifications rev 0.0 07/23/01 initial version. rev 0.1 08/20/01 1. modified dc electrical characteristics (p. 9). added x36 i dd (max) spec 750ma @ 275 mhz added x18 i dd (max) spec 700ma @ 275 mhz rev 1.0 07/03/02 1. removed x18 support. 2. modified dc recommended operating conditions (p. 7). v ddq (max) 1.9v to 1.6v v ref , v cm (max) 1.0v to 0.85v 3. modified dc electrical characteristics (p. 8). r out rq/5 10% to rq/5 15% 4. modified ac electrical characteristics (p. 9). -25 t kxch , t kxcl 1.6ns to 1.8ns -27 t kxch , t kxcl 1.7ns to 1.9ns -3 t kxch , t kxcl 1.8ns to 2.0ns t dvkh , t dvkl , t khdx , t kldx 0.25ns to 0.3ns 5. removed 1.8v v ddq ac test conditions.

▲Up To Search▲

Price & Availability of CXK77Q36162GB

	To Download CXK77Q36162GB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .